vishay siliconix dg2018, dg2019 document number: 72342 s-82626-rev. c, 03-nov-08 www.vishay.com 1 low voltage, dual dpdt and quad spdt analog switches features ? low voltage operation (1.8 v to 5.5 v) ? low on resistance - r ds(on) : 6 at 2.7 v ? low voltage logic compatible - dg2019: v inh = 1 v ? high bandwidth: 180 mhz ? qfn-16 package benefits ? ideal for both analog and digital signal switching ? reduced power consumption ? high accuracy ? reduced pcb space ? fast switching ? low leakage applications ? cellular phones ? audio and video signal routing ? pcmcia cards ? battery operated systems ? portable instrumentation description the dg2018 and dg2019 are low voltage, single supply analog switches. the dg2018 is a dual double-pole/double- throw (dpdt) with two control inputs that each controls a pair of single-pole/double-throw (spdt). the dg2019 uses one control pin to operate fo ur independent spdt switches. when operated on a + 3 v supply, the dg2018?s control pins are compatible with 1.8 v digital logic. the dg2019 has an available feature of a v l pin that allows a 1.0 v threshold for the control pin when v l is powered with 1.5 v. built on vishay siliconix?s low voltage submicron cmos process, the dg2018 and dg2019 are ideal for high performance switching of analog signals; providing low on- resistance (6 at + 2.7 v), fast speed (t on , t off at 42 ns and 16 ns), and a bandwidth that exceeds 180 mhz. the dg2018 and dg2019 were designed to offer solutions that extend beyond audio/video functions, to providing the performance required for today?s demanding mixed-signal switching in portable applications. an epitaxial layer prevents latch-up. brake-before-make is guaranteed for all spdt?s. all s witches conduct equally well in both directions when on, and blocks up to the power supply level when off. functional block diagram and pin configuration in1, in2 no4 com2 no2 nc3 in3, in4 nc1 com4 1 2 3 12 11 10 49 56 8 16 15 14 13 nc2 gnd no3 com3 com1 no1 v+ nc4 top view dg2018dn qfn-16 (3 x 3) 7 truth table in1, in2 logic nc1 and nc2 no1 and no2 0onoff 1offon in3, in4 logic nc3 and nc4 no3 and no4 0onoff 1offon ordering information temp. range package part number - 40 c to 85 c qfn-16 (3 x 3 mm) dg2018dn
www.vishay.com 2 document number: 72342 s-82626-rev. c, 03-nov-08 vishay siliconix dg2018, dg2019 functional block diagram and pin configuration notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 4.0 mw/c above 70 c. in no4 com2 no2 nc3 v l nc1 com4 1 2 3 12 11 10 49 56 8 16 15 14 13 nc2 gnd no3 com3 com1 no1 v+ nc4 top view dg2019dn qfn-16 (3 x 3) 7 truth table logic nc1, 2, 3 and 4 no1, 2, 3 and 4 0onoff 1offon ordering information temp. range package part number - 40 c to 85 c qfn-16 (3 x 3 mm) dg2019dn absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 6 v in, com, nc, no - 0.3 to (v+ + 0.3) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 100 storage temperature (d suffix) - 65 to 150 c power dissipation (packages) b qfn-16 (3 x 3 mm) c 850 mw
document number: 72342 s-82626-rev. c, 03-nov-08 www.vishay.com 3 vishay siliconix dg2018, dg2019 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. specifications v+ = 3 v parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 %, (dg2018 only) v in = 0.5 or 1.4 v e (dg2019 only) v l = 1.5 v, v in = 0.4 or 1.0 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 0.2 v/1.5 v i no , i nc = 10 ma room full 612 15 r on flatness r on flatness v+ = 2.7 v v com = 0 to v+, i no , i nc = 10 ma room 0.5 2 r on match between channels r on room 0.6 3 switch off leakage current i no(off) i nc(off) v+ = 3.3 v, v no , v nc = 0.3 v/3 v v com = 3 v/0.3 v room full - 1 - 10 0.3 1 10 na i com(off) room full - 1 - 10 0.3 1 10 channel-on leakage current i com(on) v+ = 3.3 v, v no , v nc = v com = 0.3 v/3 v room full - 1 10 0.3 1 10 digital control input high voltage v inh dg2018 full 1.4 v v l = 1.5 v dg2019 full 1.0 input low voltage v inl dg2018 full 0.5 v l = 1.5 v dg2019 full 0.4 input capacitance c in f = 1 mhz full 9 pf input current i inl or i inh v in = 0 or v+ full - 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 2.0 v, r l = 300 , c l = 35 pf room full 42 55 65 ns turn-off time t off room full 16 25 35 break-before-make time t d v no or v nc = 2.0 v, r l = 50 , c l = 35 pf full 1 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 room - 1.46 pc off-isolation d oirr r l = 50 , c l = 5 pf, f = 1 mhz room - 67 db crosstalk d x ta l k room - 72 bandwidth d bw room 180 mhz n o , n c off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 9 pf c nc(off) room 9 channel-on capacitance d c no(on) room 30 c nc(on room 30 power supply power supply current i+ v in = 0 or v+ full 0.01 1.0 a
www.vishay.com 4 document number: 72342 s-82626-rev. c, 03-nov-08 vishay siliconix dg2018, dg2019 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this data sheet. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. not production tested. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications v+ = 5 v parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 %, (dg2018 only) v in = 0.8 or 1.8 v e (dg2019 only) v l = 1.5 v, v in = 0.4 or 1.0 v e temp. a limits - 40 c to 85 c unit min. b typ. c max. b analog switch analog signal range d v no , v nc , v com full 0 v+ v on-resistance r on v+ = 4.5 v, v com = 3 v, i no , i nc = 10 ma room full 48 10 r on flatness r on flatness v+ = 4.5 v v com = 0 to v+, i no , i nc = 10 ma room 0.6 1.2 r on match between channels r on room 0.6 1.2 switch off leakage current f i no(off) i nc(off) v+ = 5.5 v v no , v nc = 1 v/4.5 v, v com = 4.5 v/1 v room full - 1 - 10 0.03 1 10 na i com(off) room full - 1 - 10 0.03 1 10 channel-on leakage current f i com(on) v+ = 5.5 v, v no , v nc = v com = 1 v/4.5 v room full - 1 - 10 0.03 1 10 digital control input high voltage v inh dg2018 full 1.8 v v l = 1.5 v dg2019 full 1.0 input low voltage v inl dg2018 full 0.8 v l = 1.5 v dg2019 full 0.4 input capacitance c in full 9 pf input current i inl or i inh v in = 0 or v+ full 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 3 v, r l = 300 , c l = 35 pf room full 44 48 52 ns turn-off time t off room full 19 33 35 break-before-make time t d v no or v nc = 3 v, r l = 50 , c l = 35 pf full 1 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 room - 2.46 pc off-isolation d oirr r l = 50 , c l = 5 pf, f = 1 mhz room - 67 db crosstalk d x ta l k room - 72 bandwidth d bw room 180 mhz source-off capacitance d c no(off) v in = 0 or v+, f = 1 mhz room 7.5 pf c nc(off) room 7.5 channel-on capacitance d c no(on) room 30 c nc(on room 30 power supply power supply range v+ 1.8 5.5 v power supply current i+ v in = 0 or v+ full 0.01 1.0 a
document number: 72342 s-82626-rev. c, 03-nov-08 www.vishay.com 5 vishay siliconix dg2018, dg2019 typical characteristics 25 c, unless otherwise noted r on vs. v com and supply voltage supply current vs. temperature leakage current vs. temperature 0 2 4 6 8 10 0123456 v com - analog voltage (v) - on-resistance ( ) r on t = 25 c i com = 10 ma v+ = 5.5 v v+ = 2.7 v v+ = 3.3 v - 60 - 40 - 20 0 20 40 60 80 100 1 1000 10 000 temperature ( c) v+ = 5.5 v v in = 0 v 10 100 i+ - supply current (pa) - 60 - 40 - 20 0 20 40 60 80 100 1 1000 10 000 temperature ( c) v+ = 5 v 10 100 leakage current (pa) i no(off) , ii nc(off) i com(off) i com(on) r on vs. analog voltage and temperature supply current vs. input switching frequency leakage vs. analog voltage 0 1 2 3 4 5 6 7 8 9 0123456 v com - analog voltage (v) - on-resistance ( ) r on v+ = 2.7 v 25 c v+ = 5.5 v - 40 c 85 c 85 c 25 c - 40 c input switching frequency (hz) i+ - supply current (a) 0 10 m 2 m 10 ma 1 a 100 na 10 na 0 1 ma 4 m 6 m 8 m 10 a 100 a - 150 - 125 - 100 - 75 - 50 - 25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v com , v no , v nc - analog voltage (v) leakage current (pa) v + = 3.3 v i no(off) , i nc(off) i com(off) i com(on)
www.vishay.com 6 document number: 72342 s-82626-rev. c, 03-nov-08 vishay siliconix dg2018, dg2019 typical characteristics 25 c, unless otherwise noted switching time vs. temperature and supply voltage v in vs. v l (typ) 0 10 20 30 40 50 - 60 - 40 - 20 0 20 40 60 80 100 r l = 300 t on v+ = 5.5 v t off v+ = 3.3 v t off v+ = 5.5 v temperature ( c) t on v+ = 3.3 v t on /t off - switching time (ns) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v l (v) v+ = 3.3 v v + = 5.5 v v th - threshold voltage dg2019 switching voltage vs. supply voltage (v+) charge injection at source vs. analog voltage 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0123456 on/off off/on v th - threshold voltage dg2018 v + - supply voltage (v) -6 -4 - 2 0 2 4 6 8 10 0123456 q - charge injection (pc) v com - analog voltage (v) v+ = 3.3 v v + = 5.5 v insertion loss, off isolation and crosstalk vs. frequency 100k 1m 100m 1g frequency (hz) x talk loss 10m v+ = 3.0 v, 5.5 v r l oirr loss, oirr, x talk (db) - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 l = 5 pf = 50 , c
document number: 72342 s-82626-rev. c, 03-nov-08 www.vishay.com 7 vishay siliconix dg2018, dg2019 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 v out gnd v+ 50 % 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output 0.9 x v out t r < 5 ns t f < 5 ns v inh v inl v out =v com r l r l +r on figure 2. charge injection off on on in v out v out q = v out x c l c l = 1 nf r gen v out com v in = 0 - v+ in v gen gnd v+ v+ in depends on switch configuration: input polarity determined b y sense of switch. + nc or no figure 3. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd c l 35 pf v o r l 50 v inl v inh
www.vishay.com 8 document number: 72342 s-82626-rev. c, 03-nov-08 vishay siliconix dg2018, dg2019 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72342 . figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v com v no/ nc r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
-c- c 0.08 notes: 1. all dimensions are in millimeters. 2. n is the total number of terminals. 3. dimension b applies to metallized terminal and is measured between 0.25 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed heat sink slug as well as the terminal. 5. the pin #1 identifier may be either a mold or marked feature, it must be located within the zone iindicated. 4 c 0.10 // -a- -b- e seating plane a3 a1 a 4 nx side view 3 3 terminal tip exposed pad d d/2 e/2 bottom view top view c 0.25 c 0.25 e2/2 e2 d2 d2/2 l e 3 x e 3 x e c 0.10 m a b 4xb package information vishay siliconix document number: 72208 29-dec-03 www.vishay.com 1 qfn?16 lead (3 x 3) variation 1 variation 2 dim millimeters inches millimeters inches min nom max min nom max min nom max min nom max a 0.80 0.90 1.00 0.031 0.035 0.039 0.80 0.90 1.00 0.031 0.035 0.039 b 0.18 0.23 0.30 0.007 0.009 0.012 0.18 0.25 0.30 0.007 0.010 0.012 d 3.00 bsc 0.118 bsc 3.00 bsc 0.118 bsc d2 1.00 1.15 1.25 0.039 0.045 0.049 1.55 1.70 1.80 0.061 0.067 0.071 e 3.00 bsc 0.118 bsc 3.00 bsc 0.118 bsc e2 1.00 1.15 1.25 0.039 0.045 0.049 1.55 1.70 1.80 0.061 0.067 0.071 e 0.50 bsc 0.020 bsc 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 0.30 0.40 0.50 0.012 0.016 0.020 ecn: s-32625?rev. b, 29-dec-03 dwg: 5899
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